1. Field of the Invention
The present invention relates to a PDP (plasma display panel) driving method. More specifically, the present invention relates to a PDP driving method for reducing a reset time.
2. Description of the Related Art
Recently, LCDs (liquid crystal displays), FEDs (field emission displays), and PDPs have been actively developed. PDPs have better luminance and light emission efficiency compared to the other types of flat panel devices, and also have wider view angles. Therefore, PDPs have come into the spotlight as substitutes for conventional CRTs (cathode ray tubes) in large displays of greater than 40 inches.
A PDP is a flat display that uses plasma generated via a gas discharge process to display characters or other images. Tens of thousands to millions of pixels may be provided thereon in a matrix format. The exact number of pixels depends on the size of the display. PDPs are either DC PDPs or AC PDPs.
Because DC PDPs have electrodes exposed in the discharge space, they allow electric current to flow in the discharge space while the voltage is supplied, and they therefore problematically require resistors for current restriction. On the other hand, because AC PDPs have electrodes covered by a dielectric layer, capacitances may naturally form to restrict the current, and the electrodes may be protected from ion shocks during discharge. Accordingly, AC PDPs have a longer lifespan than the DC PDPs.
FIG. 1 shows a perspective view of an AC PDP in general.
As shown in FIG. 1, a scan electrode 4 and a sustain electrode, disposed over a dielectric layer 2 and a protection film 3, may be provided in parallel and form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 may be provided on a second glass substrate 6. Barrier ribs 9 may be formed in parallel with the address electrodes 8 on the insulation layer 7 provided between the address electrodes 8. Also, phosphors 10 may be formed on the surface of the insulation layer 7 and on both sides of the barrier ribs 9. The first and second glass substrates 1 and 2 may be provided to face each other so that the scan electrodes 4 may cross the address electrodes 8 and the sustain electrodes 5 may cross the address electrodes 8 with discharge spaces 11 therebetween. Discharge spaces provided at crossing points of the address electrodes 8 and the scan electrodes 4 and the sustain electrodes 5 in pairs form discharge cells 12.
FIG. 2 shows a PDP electrode arrangement diagram.
As illustrated in FIG. 2, the PDP electrode has an (m×n) matrix configuration. Thus, m address electrodes A1 to Am may be arranged in the column direction. Correspondingly, n scan electrodes Y1 to Yn and sustain electrodes X1 to Xn may be alternately arranged in the row direction. For ease of discussion, the scan electrodes will be referred to as “Y electrodes” and the sustain electrodes as “X electrodes.” The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
FIG. 3 shows a conventional PDP driving waveform diagram. As illustrated, each subfield in the conventional PDP driving method has a reset period, an address period, and a sustain period.
The reset period includes an erase period, a Y ramp rising period, and a Y ramp falling period. The reset period erases wall charge states of a previous sustain discharge, and sets up the wall charges in order to perform a stable address discharge.
The address period selects cells which are turned on (ON) and are not turned on (OFF), and accumulates the wall charges at the ON cells (addressed cells.) The sustain period performs a discharge for actually displaying images on the addressed cells.
In this instance, the wall charges represent the charges which may be formed on the walls (e.g., a dielectric layer) of the discharge cells near the respective electrodes and accumulated at the electrodes. The wall charges may actually not contact the electrodes, but they may be described being “formed,” “accumulated,” or “piled” at the electrodes. Also, a wall voltage represents a potential difference formed on the wall of the discharge cells by the wall charges.
The accurate addressing operation may be generated during a subsequent address period in the conventional reset method by generating a reset discharge during the Y ramp rising period and the Y ramp falling period and controlling the quantity of the wall charges within the cell. In such a reset method, an accurate addressing operation is generated during the subsequent addressing period as a voltage difference between the Y electrode and the X electrode becomes greater during the reset period.
Because the wall charge states of the cells to which a sustain discharge has been generated and the cells to which no sustain discharge has been generated in the previous subfield may be different, the load may vary during the reset period of the subsequent subfield. That is, when a sustain discharge has been generated in the previous subfield to a large number of cells, sufficient priming particles and wall charges may accumulate in the discharge cells. Accordingly, the discharge firing voltage may be reduced in the subsequent subfield, and when a sustain discharge has been generated in the previous subfield to a small number of cells, priming particles and wall charges are rarely accumulated in the discharge cells, and hence, a discharge firing voltage is increased in the subsequent subfield.
In the conventional technique, reset pulses in the same format are necessarily applied to all the subfields during the reset period. As a result, the load variation in the reset period is not actively processed, and no stable reset operation is performed.